Höchstleistungsrechenzentrum Stuttgart: Introduction to oneAPI, SYCL2020 and OpenMP offloading

Prerequisites and content levels

Good knowlegde any of C/C++/Fortran and familiarity with usual OpenMP programming is sufficient for the OpenMP part. For Data Parallel C++/SYCL knowlegde of C++11 or later is recommended (C++17 very much faciliates SYCL2020 programming).

Content levels

Basic: 6:35 hours
Intermediate: 3:30 hours

Learn more about course curricula and content levels.

Instructors

Intel staff and GROMACS developers.

Learning outcomes

After this course, participants will:

be familiar with the oneAPI programming model,
have an overview over DPC++/SYCL programming,
have gained knowledge about fundamental OpenMP offloading,
have an overview over oneAPI libraries (oneMLK, ...),
basic knowledge about profiling and performance analysis,
basic knowlegde on (dynamical) debugging of programms using the oneAPI programming model,
be aware how Intel's Compatibility tool can help to migrate CUDA to SYCL code.

Agenda

The preliminary agenda is as follows. All times are CEST.

Day 1
Start	End
8:45	9:00	Drop in to Zoom
09:00	09:10	Welcome and Introduction to Day 1
09:10	09:30	oneAPI – Introduction to a new Development Environment - Concept and oneAPI Standardization initiative - Intel’s Tools Implementation – Intel oneAPI Toolkits and libs - Transition from Intel Parallel Studio XE to Intel oneAPI toolkits
09:30	09:50	Introduction to the DevCloud - Purpose: Demoing, testing and porting applications - Hardware and Software offerings - How to onboard & how to get an DevCloud account
09:50	10:00	Break
10:00	11:00	Direct programming with oneAPI Compilers (Part 1) – with Demos - Intro to heterogenous programming model with SYCL 2020 - SYCL features and examples o “Hello World” Example o Device Selection o Execution Model
11:00	11:15	Break
11:15	12:30	Direct programming with oneAPI Compilers (Part 2) – with Demos o Compilation and Execution Flow o Memory Model; Buffers, Unified Shared Memory (USM) o Performance optimizations with SYCL features

Day 2
Start	End
8:45	9:00	Drop in to Zoom
09:00	10:00	Intel OpenMP for Offloading – with Demos - Parallelizing heterogenous applications with OpenMP 5.1 - Mixing of OpenMP and SYCL
10:00	10:35	Intel oneAPI libraries (oneMKL) for HPC - with demos - Performance optimized libraries for numerical simulations and other purposes
10:35	10:50	Break
10:50	11:20	Intel Debugging Tools for heterogenous programming ( CPU, GPU ) - with demos
11:20	12:00	Open Source Compatibility tool for porting purposes (SYCLomatic) - with demo - Migration Cuda based GPU Applications to SYCL
12:00	12:30	Dynamic Debugging with Intel Inspector - with demos - Identifying Memory and Threading Errors (Data Races and Deadlocks)

Day 3
Start	End
8:45	9:00	Drop in to Zoom
09:00	10:10	Application profiling for heterogenous hardware - Demos - Profiling Tools Interfaces for GPU - Open Source lightweight Tools - Profile heterogenous SYCL/OpenMP Workloads with Intel VTune Profiler - Share experiences/key findings with Gromacs related porting and optimization efforts
10:10	10:20	Break
10:20	11:30	Application profiling for heterogenous hardware - Demos - Estimate performance potential gains with Offload Advisor (CPU -> HW Accelerator) - Analyse heterogenous SYCL/OpenMP Workloads with Intel Advisor and Roofline analysis
11:30	11:40	Break
11:40	12:40	A 3rd Party oneAPI Case Study: GROMACS - A Molecular Dynamics Engine - Heterogenous Design consideration, alternatives and comparisons - Real Scheduling - SYCL - oneAPI and other Implementations - SYCL in GROAMCS 2022
12:40	12:45	Break
12:45	13:10	Programming for Distributed HPC Systems using Intel MPI
13:10	13:15	- Questions and Answers - Wrap up

Exercises

In the course only demonstrations will be shown. However, we will also show how to access Intel's DevCloud where participants can explore and work on the examples given themself in the afternoon.

Registration-information

Register via the button at the top of this page.
We encourage you to register to the waiting list if the course is full. Places might become available.

Registration closes on October 12, 2022 (extended registration phase).

Late registrations after that date are still possible according to the course capacity.

Fees

This course is free of charge.

Our course fee includes coffee breaks (in classroom courses only).

Contact

Tobias Haas phone 0711 685 87223, tobias.haas(at)hlrs.de

PRACE PATC and bwHPC

HLRS is part of the Gauss Centre for Supercomputing (GCS), which is one of the six PRACE Advanced Training Centres (PATCs) that started in Feb. 2012.

HLRS is also member of the Baden-Württemberg initiative bwHPC.

This course is not part of the PATC curriculum and is not sponsored by the PATC program.

Further courses

See the training overview and the Supercomputing Academy pages.